2005. 10. 25 1/8 semiconductor technical data KMA7D0NP30Q n and p-ch trench mosfet revision no : 3 general description switching regulator and dc-dc converter applications. it s mainly suitable for power management in notebook, portable equipment and battery powered systems. features n-channel : v dss =30v, i d =7a. : r ds(on) =17m (typ.) @ v gs =10v. : r ds(on) =22m (typ.) @ v gs =4.5v. p-channel : v dss =-30v, i d =-5.5a. : r ds(on) =35m (typ.) @ v gs =-10v. : r ds(on) =51m (typ.) @ v gs =-4.5v. super high dense cell design for extermely low r ds(on) . reliable and rugged. maximum rating (ta=25 ) flp-8 b2 g h b1 0.5 max p t 1.27 millimeters 0.4 0.1 0.15+0.1/ - 0.05 4.9 0.1 b2 g h l d a b1 dim 6.0 0.2 1.5 0.2 0.75 0.2 3.9 0.1 + _ + _ + _ + _ + _ + _ 1 4 5 8 a p d l t * : surface mounted on fr4 board, t 10sec. g1 s1 d1 d1 g2 d2 d2 s2 n-channel mosfet p-channel mosfet characteristic symbol n-ch p-ch unit drain-source voltage v dss 30 -30 v gate-source voltage v gss 20 20 v drain curren dc i d * 7 -5.5 a pulsed i dp 28 -20 drain power dissipation ta=25 p d * 2 w ta=100 0.8 maximum junction temperature t j 150 storage temperature range t stg -55 150 thermal resistance, junction to case r thja * 62.5 /w 1 2 3 4 8 7 6 5 s 1 g 1 s 2 g 2 d 1 d 1 d 2 d 2 pin connection (top view)
2005. 10. 25 2/8 KMA7D0NP30Q revision no : 3 electrical characteristics (ta=25 ) note 1) pulse test : pulse width 300 , duty cycle 2% note 2) guaranteed by design, not subject to production testing. characteristic symbol test condition min. typ. max. unit static drain-source breakdown voltage bv dss i d = 250 a, v gs =0v n-ch 30 - - v p-ch -30 - - drain cut-off current i dss v ds =24v, v gs =0v n-ch - - 1 a v ds =-24v, v gs =0v p-ch - - -1 gate threshold voltage v th v ds =v gs , i d = 250 a n-ch 1 1.5 2 v p-ch -1 -1.5 -2 gate leakage current i gss v gs = 20v, v ds =0v n-ch p-ch - - 100 na drain-source on resistance r ds(on) (note 1) v gs =10v, i d =7a n-ch - 17 24 m v gs =4.5v, i d =5a - 22 30 v gs =-10v, i d =-5.5a p-ch - 35 56 v gs =-4.5v, i d =-4a - 51 78 source-drain diode forward voltage v sd (note 1) i dr =2a, v gs =0v n-ch - 0.7 1.3 v i dr =-2.3a, v gs =0v p-ch - -0.7 -1.3 dynamic (note 2) total gate charge q g n-channel v ds =15v, i d =7a v gs =10v p-channel v ds =-15v, i d =-5.5a v gs =-10v (fig.1) n-ch - 19 28 nc p-ch - 33 43 gate-source charge q gs n-ch - 1.6 - p-ch - 5 - gate-drain charge q gd n-ch - 3.6 - p-ch - 4 - turn-on delay time t d(on) n-channel v dd =15v, i d =2a v in =10v, r g =6 r l =7.5 p-channel v dd =-15v, i d =-2a v in =-10v, r g =6 r l =7.5 (fig.2) n-ch - 11 20 ns p-ch - 12 24 turn-on rise time t r n-ch - 17 28 p-ch - 15 29 turn-off delay time t d(off) n-ch - 36 62 p-ch - 35 60 turn-off fall time t f n-ch - 20 36 p-ch - 15 30 input capacitance c iss n-channel v ds =25v, v gs =0v f=1.0mhz p-channel v ds =-25v, v gs =0v f=1.0mhz n-ch - 835 - pf p-ch - 950 - reverse transfer capacitance c rss n-ch - 15 - p-ch - 110 - output capacitance c oss n-ch - 145 - p-ch - 160 -
2005. 10. 25 3/8 KMA7D0NP30Q revision no : 3 gate - source voltage v gs (v) i d - v ds drain - source voltage v ds (v) 0 0 20 25 30 5 15 10 0 10 15 30 5 20 25 15 3 24 01 5 3 24 i d - v gs v th - t j r ds(on) - i d r ds(on) - t j -75 -50 -25 0.2 0.6 0.4 0.8 1.6 1.0 1.2 1.4 050 25 100 150 75 125 drain current i d (a) drain current i d (a) i s - v sd 0.0 1 10 0.1 30 0.2 0.6 1.0 1.4 1.2 0.8 0.4 0 35 5 10 40 30 25 15 20 0 5 30 25 10 20 15 25 -25 50 -75 -50 100 150 125 75 v gs = 4, 5, 6, 7, 8, 9, 10v v gs = 10v v gs = 4.5v 1.4 0.6 0.4 0.8 1.0 1.2 1.8 1.6 normalized threshold voltage v th (v) drain current i d (a) on - resistance r ds(on) (m ? ) reverse drain current i s (a) junction temperture t j ( ) normalized on resistance junction temperature tj ( ) c source - drain voltage v sd (v) c i ds = 250 a v gs = 10v i ds = 7a v gs =3v v gs =2v tj= -55 c tj=25 c tj=125 c tj=25 c tj=150 c n-channel
2005. 10. 25 4/8 KMA7D0NP30Q revision no : 3 drain current i d (a) gate - charge q g (nc) c - v ds drain - source voltage v ds (v) drain - source voltage v ds (v) square wave pulse duration ( sec ) 0 10 6 2 4 8 8 20 4 16 12 0 q g - v gs safe operation area capacitance (pf) normalized transient thermal resistance gate - source voltage v gs (v) 0 200 600 800 1000 1200 1400 400 020 10 30 10 -4 1ms 10ms 100ms 1s dc rth 10 -3 10 -3 10 -2 10 -1 10 -1 10 0 10 0 10 -2 10 1 10 -2 10 -1 10 0 10 1 10 2 10 -2 10 -1 10 0 10 1 10 2 mounted on fr4 board r thja : 62.5 /w c duty=0.5 singl e p ulse 0.01 0.02 0.05 0.1 0.2 c iss c oss c rss r ds(on) limit ta= 25 c frequency=1mhz v ds =15v i ds =7a 300 s 3 0 0 s
2005. 10. 25 5/8 KMA7D0NP30Q revision no : 3 gate - source voltage v gs (v) i d - v ds drain - source voltage v ds (v) 0 0 -16 -20 -24 -4 -12 -8 0 -4 -6 -2 -8 -10 -14 -16 -12 -18 -20 -22 -2 -10 -6 -4 -8 0-1 -5 -3 -2 -4 i d - v gs v th - t j r ds(on) - i d r ds(on) - t j -75 -50 -25 0.00 -0.50 -0.25 -0.75 -1.75 -1.00 -1.25 -1.50 050 25 100 150 75 125 drain current i d (a) drain current i d (a) i s - v sd 0.0 -1 -10 -0.1 -0.2 -0.6 -1.0 -1.4 -1.2 -0.8 -0.4 0 70 80 10 40 30 60 50 20 0 -4 -24 -20 -8 -16 -12 25 -25 50 -75 -50 100 150 125 75 v gs =-10v v gs =-4.5v 1.4 0.6 0.4 0.8 1.0 1.2 1.8 1.6 normalized threshold voltage v th (v) drain current i d (a) on - resistance r ds(on) (m ? ) reverse drain current i s (a) junction temperture t j ( ) normalized on resistance junction temperature tj ( ) c source - drain voltage v sd (v) c i ds = - 250 a v gs = -10v i ds = -5.5a v gs = -5,-6,-7,-8,-9,-10v v gs =-4v tj= -55 c tj=25 c tj=125 c v gs =-3v tj=25 c tj=150 c p-channel
2005. 10. 25 6/8 KMA7D0NP30Q revision no : 3 drain current i d (a) gate - charge q g (nc) c - v ds drain - source voltage v ds (v) drain - source voltage v ds (v) square wave pulse duration (sec) 0 -10 -6 -2 -4 -8 -9 -5 -1 -3 -7 20 10 30 15 535 25 0 q g - v gs safe operation area capacitance (pf) normalized transient thermal resistance gate - source voltage v gs (v) 0 250 750 1000 1500 1250 500 0 - 20 - 10 - 30 -0.01 -0.1 -1 -10 -100 -0.01 -0.1 -1 -10 -100 10 -4 10 -3 10 -3 10 -2 10 -2 10 -1 10 -1 10 0 10 0 10 1 1ms 10ms 100ms 1s dc rth duty = 0.5 single pulse 0.01 0.02 0.05 0.1 0.2 c iss c oss c rss r ds ( o n) limit ta= 25 c frequency=1mhz v ds = - 15v i ds = - 5.5a mounted on fr4 board r thja : 62.5 /w c
2005. 10. 25 7/8 KMA7D0NP30Q revision no : 3 fig. 1 gate charge v gs 10 v q g q gd q gs q v ds v gs t r t d(on) 10% 90% t on t f t d(off) t off n -channel i d i d fig. 2 resistive load switching v ds v gs v ds v gs 1.0 ma schottky diode 10 v 6 ? r l 0.5 v dss 0.5 v dss
2005. 10. 25 8/8 KMA7D0NP30Q revision no : 3 v gs - 10 v q g q gd q gs q v ds v gs t r t d(on) 10% 90% t on t f t d(off) t off p -channel fig. 1 gate charge i d i d fig. 2 resistive load switching v gs v ds v gs 1.0 ma schottky diode - 4.5 v 6 ? r l 0.5 v dss 0.5 v dss v ds
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